A Design of Power Amplifier With Digitally Gate Bias Control for Dual-Band Dual-Power-Mode Operations in 65-nm CMOS Technology

This letter presents a novel power amplifier (PA) architecture employing load-line theory and a reconfigurable output matching network. The proposed design achieves low-/high-power (LP/HP) modes across two distinct frequency bands with digitally gate bias control units. This design achieves four-mode control with only two digitally controlled switches to reduce complexity. Fabricated in TSMC’s 65-nm CMOS process, the chip demonstrates measured saturated power-added efficiency (PAE) of 43.1%–52.7% in the HP mode and 33.7%–44.6% PAE at 7-dB back-off in the LP mode across 0.4–1 GHz, with a fractional bandwidth of 85.7%. The proposed architecture achieves a saturated output power of 17.0–18.0 dBm across 0.4–1 and 1.8–2.5 GHz while maintaining a compact die area of 0.82 mm², offering a high-efficiency solution for multiband transceiver applications.