Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET

For the first time, this study presents two novel vertical FET (VFET) structures and conducts a quantitative analysis to assess the competitiveness of VFET in comparison to two types of horizontal FET (HFET) which are nanosheet FET (NSFET) and forksheet FET (FSFET) targeting Angstrom nodes. The conventional VFET (VFETCON) design exhibits a larger footprint than FSFET, delivering an inferior performance even when optimized for gate length. By contrast, the novel fork-shaped channel VFET (VFETFS) demonstrates a 10.5% reduction in the effective area compared to VFETCON, achieving a smaller footprint than FSFET with a large contact poly pitch (CPP). Additionally, $\mathrm { VFET_{FS}}$ offers enhanced performance over $\mathrm { VFET_{CON}}$ due to reduced capacitance. However, $\mathrm { VFET_{FS}}$ shows more effective area and has a significantly lower drive current (Ion) than FSFET with a small CPP. Strategies to expand the silicide area effectively improve $\mathrm { I_{on}}$ by reducing parasitic resistance, enabling NFET $\mathrm { VFET_{FS}}$ to outperform FSFET. However, for PFET, $\mathrm { VFET_{FS}}$ employing enlarged silicide areas exhibits lower performance compared with FSFET owing to the more substantial impact of performance degradation under non-stress conditions. The secondary device architecture, $\mathrm { VFET_{FS}}$ with back-side contact (VFETBSC), further decreases the footprint, significantly lowers parasitic RC, and shows great heat dissipation when it has a large BSC area. $\mathrm { VFET_{BSC}}$ requires a smaller effective area than FSFET with a 42 nm CPP, and its average performance for N/PFET surpasses that of FSFET.