Fpga Implementation of a Novel Multiple-Image Encryption Algorithm

This paper presents a Field Programmable Gate Arrays (FPGA) implementation of a novel multiple-image encryption algorithm that combines an 8-dimensional (8D) hyperchaotic system, Josephus permutations, process queues, and Rule 30 cellular automata (CA) to achieve robust security and efficiency. The encryption framework employs three stages of key generation and image permutation, each with distinct strategies to scramble pixel positions and ensure strong resistance to cryptanalytic attacks. Multiple plain images are converted into 1D bit-streams and encrypted using XOR operations with dynamically generated keys, ensuring both diffusion and confusion. The FPGA implementation demonstrates a high-speed performance, of 0.8 Gbps, and low resource utilization, making it ideal for real-time and resource-constrained applications. Experimental results confirm the algorithm's encryption quality, key sensitivity, vast key space of 2⁷⁹⁷², and attack resistance, highlighting its potential for secure image transmission in modern communication systems.