Efficient Routing Congestion Prediction in Chip Design: Integrating Netlist Structure and Design Specifications With Heterogeneous Graph Attention Networks

Routing congestion is a critical concern that detrimentally impacts chip performance, necessitating substantial time investment in detection and alleviation during the chip design process. Predicting congestion on the netlist significantly reduces time consumption by obtaining routing feedback immediately after design completion without going through subsequent steps. However, the constraints on chip production imposed by design specifications significantly influence routing, and it is ignored by previous studies, resulting in imprecise predictions and sub-optimal optimization. In this study, we design a heterogeneous graph introducing the influence of design specifications to aid netlist congestion prediction. Subsequently, we develop a heterogeneous graph attention network that uses a two-level attention mechanism to capture the effects of netlist structure and design specifications. Experimental results demonstrate our method achieves fast and accurate congestion prediction with up to 19% accuracy improvement and 5.22× prediction speedup. To the best of our knowledge, it is the first work that integrates design specifications, enabling a comprehensive prediction of congestion arising from both the netlist structure and the design specifications.