Advances and Exciting Prospects in Forksheet FET Technology for Sustainable Scaling for Future Analog/RF and Digital Integrated Circuit Applications: A Review

The silicon (Si) fin-field-effect-transistor (FinFET) technology revolutionized the semiconductor industry by enabling scaling down to the advanced 4-nm node. Even FinFET has limitations, though, as it is difficult to scale down to the sub-3-nm node due to the short channel effects (SCEs) and the higher fin aspect ratio brought on by fin depopulation. These challenges can be alleviated by a nanosheet FET (NSFET), a next-generation technology that can replace FinFET due to its vertically stacked horizontal channels and superior gate controllability. However, NSFETs still face key hurdles—most notably, the spacing between p-type and n-type FETs, which limits further scaling. Reducing the spacing between nFET and pFET necessitates a gate cut with a high aspect ratio, which can also introduce challenges, such as mask undercutting during work-function metal (WFM) patterning. A fork-shaped FET (FSFET) addresses these challenges by introducing a dielectric wall (DW) between the nFET and pFET, enabling a significant reduction in logic cell height. This article provides a comprehensive exploration of FSFET technology, beginning with the challenges in FET scaling and also covers the performance analysis of FSFETs, challenges and advances in fabrication, and exciting prospects in integrated circuit (IC) design and reliability issues.