The ESD Robustness of Schottky-Gate p-GaN HEMT Under Different States

This work systematically investigates the electrostatic discharge (ESD) robustness of Schottky-gate p-GaN high electron mobility transistors (HEMTs) under different gate and drain bias conditions. Gate-terminal ESD robustness is severely compromised under high ${V}_{\text {DS}}$ ( $\ge 40$ V), where synergistic high voltage/current induces thermal runaway, causing irreversible damage. At ${V}_{\text {DS}} =5$ –30 V, trap-dominated ${V}_{\text {TH}}$ shifts (up to 0.68 V) correlate with $1200\times {N}_{\text {it0}}$ increases, partially recoverable over time. With the drain in the floating state, the trap-dominated ${V}_{\text {TH}}$ shift (about 0.47 V) correlate with $140\times {N}_{\text {it}}$ increases, nearly fully recoverable over time. Under the drain-terminal ESD events, the device with the gate in floating state exhibits superior ESD robustness, accompanied by only a 0.12-V negative ${V} _{\text {TH}}$ shift and high ${V}_{\text {HBM}}$ of over 8.61 kV. The devices with gate biased at off/semi-on/on states achieve ${V}_{\text {HBM}}$ from 0.27 to 30 kV, with (semi-on) on-state configurations meeting 2-kV industrial standards. This work bridges the gap in understanding multistress ESD interactions, providing critical insights for optimizing p-GaN HEMT reliability.