FPGA-Based Visually Lossless JPEG XS Image Encoder Architecture Design and Hardware Verification

JPEG XS, as a next-generation lightweight visually lossless compression standard, has emerged as a critical technology in real-time video transmission systems due to its low computational complexity, sub-millisecond system latency, and adjustable compression ratio ranging from 2:1 to 6:1. However, traditional CPU/GPU-based implementations exhibit significant limitations in energy efficiency and real-time performance. This study proposes an FPGA-oriented hardware acceleration architecture for JPEG XS encoders, achieving dual improvements in high performance and low latency through an algorithm-hardware co-optimization strategy. The designed hardware acceleration architecture employs multi-stage pipelining and parallelization to enhance data throughput efficiency. Internally, it introduces a 5/3 wavelet transform architecture with 5×5 matrix parallel computation and optimizes the entropy coding module for parallel processing to minimize latency. Experimental results on the Xilinx XC7K410T FPGA platform demonstrate that the encoder occupies 15.6k LUTs (Look-Up Tables) and 22.54k registers, with dynamic power consumption stabilized at 0.386 W. Testing data confirms that the system achieves real-time encoding performance for 4K 70 fps, with end-to-end latency strictly controlled within 8 line cycles. This work provides an effective hardware solution for real-time video transmission systems.