A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis

Dopant freeze-out severely increases the bulk resistance of cryogenic bulk CMOS transistors by up to $10{^{{6}}} {\times }$ at 4.2K compared to room temperature. This brief describes, for the first time in the literature, how this increased bulk resistance introduces a memory effect in the latch of dynamic comparators, which leads to hysteresis. To measure this hysteresis reliably in the presence of noise, a statistical characterization procedure is developed. For a 40nm bulk CMOS strongARM comparator with an input-referred noise voltage of 348 $\mu $ VRMS, a hysteresis voltage >898 $\mu $ V is measured at 6K, substantially deteriorating the precision. Therefore, this brief introduces a triple tail comparator with capacitive over-neutralization to increase the preamplification gain, suppressing the hysteresis > $6{\times }$ to only 141 $\mu $ V.