Capacitance Degradation of SiC MOSFETs Under Dynamic Reverse Bias Stress: Displacement Current-Induced Charge Injection and JFET Design Optimization

This study investigates the capacitance degradation phenomenon in Silicon Carbide (SiC) MOSFETs under Dynamic Reverse Bias (DRB) stress, revealing a novel mechanism where the synergistic effect of displacement current and high electric field induces positive charge injection into the oxide layer. For the first time, it is discovered that the reverse transfer capacitance $(\mathbf{C}_{\mathbf{rss}})$ increases logarithmically with the number of stress cycles, while static parameters such as threshold voltage and ON-resistance remain stable (with variation rates <3%). The research confirms that during DRB, the displacement current generated by the transient drain voltage follows two distinct paths: 90% of the current flows through the N epilayer-Pwell junction (Path 1), while 10% penetrates the gate oxide above the JFET region (Path 2). The latter, combined with the high electric field in the oxide layer above the JFET region (2.26MV/cm), leads to an increase in oxide layer positive charge density, ultimately causing the increase in the $\mathbf{C}_{\mathbf{rss}}$. By optimizing the device structure and reducing the JFET region width from 1.7μm to 1.5μm, the degradation rate of $\mathbf{C}_{\mathbf{rss}}$ is reduced by 23.0%. This study provides a theoretical model and design optimization guidelines for the reliability design of SiC devices in high-frequency applications.