Analysis on BVDSS Outlier Chips and Screening Technology for 1.2 kV Automotive SiC MOSFETs

Systematic investigation combined experimental analyses and numerical simulations were conducted to determine the failure mechanism with $\text{BV}_{\mathrm{D}\mathrm{S}\mathrm{S}}$ outlier chips of 1.2 kV SiC MOSFET. A strong correlation was identified between device failure and pit defects in the epitaxial layer. When a pit is located on the P-body, significant deformation of the implantation region can be observed. The localized electric field at the corner of deformed P-body increases, which ultimately leads to premature avalanche breakdown. A screening technology was implemented, over 96% of the unqualified chips have non-killer material defects, with pits accounting for the highest proportion. After screening, the HTRB burn-in failure rate of 1,700 power modules decreased by nearly one order of magnitude. Additionally, the structure of these pits was studied, which is expected to fundamentally improve the yield of $S$iC MOSFET through epitaxial surface planarization.