Dynamic Current Balancing Methodfor Parallel SiC MOSFETs Based on Threshold Voltage Sorting underAsymmetric Layout

Silicon carbide (SiC) MOSFETs, with their outstanding performance, have found wide applications in high-frequency and high-temperature fields, particularly demonstrating significant potential in power electronics and power conversion. However, when used in parallel applications at high current levels, the current distribution between parallel chips becomes uneven due to variations in circuit and chip parameters. This leads to differences in junction temperatures between parallel chips, which, in severe cases, can cause reliability issues and result in chip failure. To mitigate the current imbalance between parallel chips, this paper first analyzes the dynamic current distribution characteristics of parallel chips under asymmetric layouts. A dynamic current balancing method for multi-chip parallel SiC MOSFETs based on threshold voltage sorting is then proposed. This method utilizes the dispersion of the threshold voltages of the chips to group them, thereby reducing the dynamic current imbalance between parallel chips. The effectiveness of this method for multichip current balancing is verified through simulations. Finally, the proposed method is validated through experiments, where in the double-pulse simulation and Buck tests, the dynamic current imbalance is reduced from 9.65A to 6.94A and from 13.69A to 5.33A, respectively. Both simulation and experimental results demonstrate that threshold voltage sorting significantly improves the current balancing performance of parallel SiC MOSFETs.