Gate Capacitor and PCB Capacitance Design for Improved Double Pulse Test of SiC MOSFETs

The double pulse test (DPT) configuration plays a critical role in the dynamic characterization of SiC MOSFETs due to their high dv/dt and di/dt rates. This paper investigates the impact of gate capacitors and printed circuit board (PCB) parasitic capacitance on DPT performance for SiC MOSFETs through simulation, theoretical analysis, and experiment. Results reveal that gate capacitors can induce resonant loops, causing oscillations during turn-on, while PCB parasitic capacitance affects the switching performance by altering the switching current and slowing down the dv/dt rate. To validate these findings, two PCB designs with different parasitic capacitances were developed, and a 600 V DPT was conducted. Experimental results demonstrate that removing the gate capacitor can effectively eliminate gate-loop oscillations and prevent unintended device failures, while minimizing PCB parasitic capacitance can suppress severe turn-on current overshoot. The optimized PCB design achieves a super-fast switching speed with 50 ns turn-on time and 40 ns turn-off time, delivering improved DPT waveforms of superior quality.