Simultaneous Power and Signal PCB Routing Considering Complex Clearance Constraints With Arbitrary Wire Widths

Automatic printed circuit board (PCB) routing is essential to handle modern PCB designs with fast-growing problem sizes and complicated design constraints. Previous PCB routing studies have two major limitations: they consider uniform wire widths and keep-out distances (clearance rules) across all elements within the same layer. However, in modern PCB design, the mixed layout of high-current power wires and signal wires makes vastly different wire widths and complex clearance conditions issues that need to be addressed. Besides, irregular component shapes and special requirements for power loops impose more challenges. This paper presents a new PCB routing algorithm based on A*-search to handle these issues effectively. A frontier-checking method is proposed to efficiently verify whether the grid violates the complex clearance rules of any wire widths during routing. Besides, we propose a scheme to divide multi-pin nets in order to reduce the total wire length while effectively handling power-related constraints. Experimental results show that our routing algorithm significantly outperforms a state-of-the-art PCB router in terms of routability, total wire length, and runtime. Moreover, our algorithm achieves human-level performance and significantly outperforms Altium on the industrial benchmark.