A Low-Power and High-Efficiency Neural Network Based Scheme for Nonlinearity and Memory Effects in Single-Channel ADCs

This work introduces a Memory-Aware Gray-Box Neural Network (MAGB-NN) for Analog-to-Digital Converter (ADC) calibration. Three key techniques are utilized to simultaneously ensure high efficiency and low hardware cost. First, the ADC is treated as a gray-box system, where prior knowledge of ADC characteristics is utilized to optimize input-layer weights, thereby reducing both network complexity and convergence time. Second, a recurrent layer is incorporated to retain prior information, enabling compensation for memory effects in high-speed ADC operation. Third, replacing multipliers with multiplexers in the output layer significantly reduces hardware overhead. A 14-bit 2.6GS/s pipeliend ADC and a 14-bit 60MS/s split pipeliend-SAR ADC are utilized to verify the proposed calibration algorithm. This approach exhibits an improvement of over 13 dB in Spurious-Free Dynamic Range (SFDR) of both ADCs. The hardware feasibility of the algorithm is verified by the FPGA and TSMC 28nm process. The experimental results show that the proposed ADC calibrator only has an area of $ 50600~{\mu }$ m2 and only consumes 7.86 mW at 1 GHz clock rate.