Efficient Power-and Area-Optimized 800-Spin Ising Chip for Solving Combinatorial Optimization Problems Using Multi-Run Decremental Annealing

This paper presents a very-large-scale-integration (VLSI)-based multi-run decremental annealing (MRDA) accelerator for solving combinatorial optimization problems (COPs). The proposed Ising chip, which features 800 spins, utilizes MRDA to minimize hardware area while maintaining high accuracy. The proposed method utilizes a local energy calculation approach, which replaces total energy computations and effectively reduces redundancy in such fully connected models. The multi-threaded design improves speed while lowering power and area overheads. Extensive tests on the Gset dataset and Max-Cut problems demonstrate that the proposed method achieves rapid convergence to near-optimal solutions, ensuring both high accuracy and low energy consumption. Fabricated using Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm process the chip runs at 91MHz, with a core area of 2.4mm2 and power consumption of 9.4mW. This design demonstrates superior efficiency and accuracy in solving complex COPs.