A Regression-Based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA Tiles

This work addresses the challenges of estimating the area, delay, and power characteristics of standard cell based FPGA tiles. The area, delay and power characteristics of standard cell based FPGA tiles are typically complicated by non-uniform cell composition and sizes due to synthesis optimizations. Traditional methods that rely on summing the area, delay and leakage power consumption of individual components in FPGA tiles face difficulties because they require accurate determination of cell sizes and compositions first. Automated cell sizing approaches have been proposed to tackle this issue, but they often require refinement when new process technologies are introduced. Additionally, running transistor sizing algorithms across a large number of architectures is computationally intensive and time-consuming. In contrast, our approach investigates a holistic regression-based methodology that directly estimates the area, delay and leakage power of an FPGA tile based on its architectural parameters. By utilizing a regression-based model, a small sample of the design space can be synthesized to create a generalized model that can be used to bypass the complex cell sizing and selection process for the remaining designs. This allows for efficient and scalable estimation that adapts more readily to new technologies and architectures without the need for extensive re-synthesis or optimization runs.