A 3.4-GS/s 12-Bit Time-Interleaved Pipelined SAR ADC With Non-Foster Ring Amplifier-Based High-Linearity Track-and-Hold Amplifier

This brief presents a 3.4-GS/s 12-bit time-interleaved pipelined SAR ADC fabricated in 28-nm CMOS, incorporating a high-linearity track-and-hold amplifier (THA) based on the proposed non-Foster ring amplifier (NFRA). By leveraging inter-stage delay reduction and feedback factor compensation based on non-Foster capacitors (NFCs), the proposed NFRA enables fast and stable settling while preserving high linearity, effectively overcoming the stability limitations of conventional ring amplifiers (RingAmps). The prototype ADC achieves 57.3-dB SNDR and 77.6-dB SFDR at near-Nyquist input, while maintaining 53-dB SNDR and 73.2-dB SFDR up to 3.5 GHz with a total power consumption of 92 mW.