BYOD: A System-Level Simulator Framework for End-To-End Evaluation and Architecture Design of Photonic AI Accelerators

Photonic AI accelerators have emerged as a promising concept for addressing the scalability and sustainability issues associated with current AI models. By processing information with analog optical signals in integrated photonics circuits (Fig. 1a), photonic accelerators promise orders-of-magnitude improvement in compute speed and energy efficiency for multiply-accumulate (MAC) operations. [1]. However, while a lot of research is focused on the photonic design, it is still challenging to develop accelerator devices that can exploit these benefits on the system level for end-to-end computations of AI workloads [1], [2]. While photonics is inherently suitable for MAC operations, accelerators still require complementary electronic circuits, e.g., for memory, communication and arithmetic operations, that can potentially offset the efficiency and speed of photonic MAC operations. For realizing the advantages of photonic computing, it is thus crucial to carefully design opto-electronic accelerator architectures (Fig. 1b) [2]. To efficiently design and evaluate such architectures, we demonstrate the BYOD (Build&Benchmark Your Optical Device) system-level simulator framework. As shown in Fig. 1c, BYOD imports models from common AI libraries and maps them to a configurable accelerator architecture. Here, components shown in Fig. 1b exist as modular simulators that can be flexibly interconnected and configured. The end-to-end data flow of the AI model is then simulated on this architecture, and energy, throughput and inference accuracy are evaluated on a cycle-accurate basis. As a proof-of-concept, we demonstrate the functionality of BYOD with a 32-neuron 2-layer optical neural network for the Iris dataset in Fig. 1d-f. Here, BYOD is used to evaluate the inference accuracy (Fig. 1d) and power consumption (Fig. 1e). These results show that power consumption is dominated by the electronic components, highlighting the need to optimize their performance. In Fig. 1f, we explore the trade-off of reducing the analog-digital conversion bit resolution and find that its energy consumption can be halved without considerable loss in accuracy until a resolution of 8 bits. To facilitate such design explorations for complex architectures, BYOD is designed to be scalable and interoperable with established simulator systems. BYOD is built using the SST simulator framework [3], which enables simulation of large-scale architectures with thousands of components within a few seconds (Fig. 1g), while also being compatible with many established tools for simulating digital computers and HPC systems [3]. With this, BYOD can facilitate an efficient system-level design of opto- electronic architectures and allows for a more accurate evaluation of the benefits of photonic AI accelerators.