Enabling Efficient Pure-NMOS Circuits Through Adiabatic Complementary Pass-Transistor Logic

For many emerging computing technologies, such as wearable and flexible IoT devices, power and energy consumption may be of far greater importance than performance and operating frequency. For some of the novel processes that underpin these technologies, efficient P-type transistors are not yet available and hence pure-NMOS logic is required. In this paper, we show that adiabatic (or reversible) logic provides an attractive solution for such technologies. We investigate the feasibility of applying Adiabatic Complementary Pass-transistor Logic (ACPL) to pure NMOS implementations and verify through simulation that the energy dissipation of a Carry Look-ahead Adder (CLA) can be reduced to less than 1% of that required by conventional NMOS logic. Furthermore, we propose a novel 2-phase ACPL named ACPL-2, which uses the same clock source as the 4-phase version but reduces the number of transistors of a binary counter by 21 % without affecting the overall energy consumption.