Improved High-Radix Carry-Save Adders for Low-Latency Vector Reduction on Fpga

Efficient summation of multiple inputs is critical in many FPGA-based applications, requiring optimized arithmetic units for reduced latency and resource utilization. This paper explores the high-radix carry-save (HRCS) format and proposes a novel carry chain architecture to improve latency. Moreover, a vector reduction operation using the improved HRCS adders is presented to highlight the impact of the low-latency HRCS adder on high-scale integer additions. Experimental results show that the improved HRCS adder achieves significant delay reductions of up to 29.5 % for the vsum 32 in radix- 64 format while maintaining nearly the same LUT utilization as the baseline design. Notably, vsum32 enables summation of up to 32 operands on FPGA in less than 4 ns, showcasing the effectiveness of the proposed HRCS adder in high-speed arithmetic applications with optimized resource efficiency.