Bi-Linearity of Back Gated Schottky Barrier Transistors on an Industrial 22nm FDSOI Platform for Efficient In-Hardware Matrix-Vector Multiplication and Addition

Machine Learning and AI approaches have stretched traditional hardware to its limits. In-hardware computing is a novel approach that aims to run Matrix-Vector Multiplication operations directly at the device level for increased efficiency. This work shows that the current of a back-bias Schottky barrier transistor built on an industrial 22nm FDSOI platform responds linearly to changes in either the source-gate or the source-drain voltage. This bi-linearity, alongside the access to independent biasing through the back gate, which allows analog vector addition directly at the device level, has great potential for in-hardware computation. The performance and multilevel operation is demonstrated by simulating a $2 \times 2$ crossbar array, which successfully performs matrix-vector multiplication and addition. The simulations employ a Verilog-A table model of actual industrial devices, highlighting the potential to integrate these devices into hardware accelerators in the short term.