A Robust Fully Differential MAC Scheme Using Dummy Rows to Enhance the Signal Margin of Analog Compute-in-Memory Architecture

In multi-bit analog compute in-memory (CIM) architecture, inadequate signal margin (SM) between two consecutive multiplication and accumulate voltages is a major problem for robust MAC operation. A robust fully differential multi-bit analog multiplication and accumulate (FDMAC) scheme using dummy rows to enhance the signal margin is proposed in this paper. The proposed scheme achieves 1.42×, 2.86×, 7.27×, and 12.8× higher SM than state-of-the-art. The proposed scheme achieves robust MAC operation with variability (σ/µ) of 3%, which is 2.87× and 3.23× lower than reported works. The energy-efficiency of proposed architecture is 2.5 TOPS/W at 1 V supply voltage in 65 nm CMOS technology. The inference accuracy of the architecture is 98.6 % and 84.73% for MNIST and CIFAR-10 dataset respectively for LeNet-5 CNN model. The Figure of Merit (FoM) of proposed architecture is 33.33, which is 2.7×, 4.9×, 5.3×, 12×, and 26.2× higher than the reported works.