A Low Power Fully Analog MAC Operation Using Standard CMOS Technology for Neural Network Inference

This paper presents a novel approach for implementing two-quadrant Multiply-Accumulate (MAC) operations entirely in the analog domain, eliminating the need for dedicated storage of negative weights. This circuit is fully compatible with standard CMOS fabrication technology. MAC operations constitute the predominant workload in Neural Networks (NNs), accounting for over 99 % of operations; thus, enhancing their efficiency is critical for advancing neural network implementations. Our proposed fully analog MAC cell leverages bulk-modulated PMOS transistors in the sub-threshold region. Using an innovative method for two-quadrant multiplication, the design achieves remarkable energy efficiency, with a consumption of only 0.92 pJ per MAC operation in 65nm technology and 0.92 pJ per inference in MNIST digit classification tasks.