A New Ultralow-Voltage Retention SRAM Cell Enhancing Noise Immunity

A new ultralow-voltage retention (ULVR) SRAM cell is proposed, which can highly enhance the noise margin (NM) for the ULVR mode at ultralow voltages $(V_{\mathrm { UL}})$ . This 8T cell is configured with new-type Schmitt-trigger (ST) inverters that can nearly maximize the hysteresis width of the voltage transfer characteristics (VTC). The design methodology of the cell is developed with careful consideration for the process variation of the constituent transistors, and the optimally designed cell can ensure sufficient NMs that satisfy the $6\sigma $ failure probability for all the operating modes. In particular, for the ULVR mode at $V_{\mathrm { UL}} {=} 0.2$ V, the proposed 8T cell can exhibit much stronger noise immunity than previously proposed various low-voltage cells. In addition, the proposed 8T cell can achieve stable data retention even at $V_{\mathrm { UL}} {=} 0.16$ V with sufficient noise immunity satisfying the $6\sigma $ failure probability. An 8kB ULVR-SRAM macro configured with the proposed-8T-cell array is also developed. Using the ULVR mode, the macro can reduce the standby power by ~93% compared with the standby mode of a conventional 6T-SRAM macro.