An 80-Gb/s PAM-4 1-to-2 Analog Demultiplexer With Time-Interleaved Track-and-Hold Amplifier in 28-nm CMOS

This letter presents a high-speed 1-to-2 analog demultiplexer (ADEMUX) with time-interleaved track-and-hold amplifiers (THAs) based on switched source follower (SSF) topology. A cross-feedthrough cancellation (CFC) technique is proposed to cancel the signal feedthrough. Clock-controlled auxiliary transistors are also introduced to cancel the clock feedthrough. Measurement results show that the ADEMUX achieves a track-mode bandwidth of 26.8 GHz, and a total harmonic distortion (THD) of −32.5 dB at 40-GS/s sampling rate, which supports up to 80-Gb/s PAM-4 data transmission. The ADEMUX was fabricated in a 28-nm CMOS process with a core area of 0.18 mm² and power consumption of 65.7mW from a 0.9-V supply.