Accelerating CRS Format Conversion for Sparse Matrix Computation with an FPGA

The Compressed Row Storage (CRS) format is widely used to enhance memory efficiency in sparse matrix computations. Still, its conversion process remains a significant performance bottleneck due to irregular memory access. This study presents an FPGA-accelerated CRS conversion pipeline implemented on an AMD Alveo U280 FPGA, leveraging high-bandwidth memory (HBM) and direct memory access (DMA) for efficient data handling. Experimental results demonstrate a 3.22× speedup over PETSc, a widely used CPU-based sparse matrix computation library, while 87.44% of total latency originates from system overheads. These findings highlight the need for further data transfer and system integration optimizations.