A Novel De-Mirroring Approach for Capacitance and Resistance Extraction in Complementary FET: A Quasi-Static Small Signal Model

A quasi-static small signal model is vitally important to bridge the gap in device circuit co-design. To the best of our knowledge, for the first time in this paper, we proposed the small-signal model of a Complementary FET (CFET) with the accurate extraction of capacitance and resistances using de-mirroring approach. Unlike conventional approach, de-mirroring considers the drain voltage ($\mathrm{V}_{\mathrm{DS}}$) dependent capacitances separately. The extracted overall gate capacitance ($\mathrm{C}_{\mathrm{gg}}$) is $10.03 \%$ lower than the mirroring approach. The various components of resistances and capacitances are modeled using the transmission line method (TLM) and conformal mapping (CM), where the model data shows the error of less than $4 \%$ with the simulation data.