Balancing Performance and Cost—FPGA-Based CNN Accelerators for Edge Computing: Status Quo, Key Challenges, and Prospective Innovations

The development of AI accelerators for real-time edge computing applications is a robust and ever-growing field that offers countless improvements upon classical CPU, GPU, or ASIC-based designs. In 2023, the edge AI accelerator market was valued at nearly 6 billion with a compound annual growth rate (CAGR) of 30.4% over the next ${\$}6$ years. However, there are currently many limitations present in the designs that have been proposed. This paper presents a comprehensive overview of FPGA-based CNN accelerators, their architectural innovations, real-world deployments, and optimization techniques. These accelerators are highly applicable for countless edge computing applications including smart surveillance systems, autonomous vehicles, traffic monitoring systems, and drone applications. Through comparative analysis, we extract key trade-offs between power consumption, throughput, hardware resource utilization, and system cost. This work not only covers architectural design strategies but also introduces a scoring framework for low-cost designs. Based on how each low-cost system performs in a specific performance field, a final score is determined. These scores allow us to identify key performance trends amongst low-cost designs, proposing solutions for the future development of such systems. Overall, our findings show that dynamically reconfigurable FPGA architectures offer appealing adaptability and performance for edge computing, at the expense of increased complexity and power consumption. Alternatively, static accelerators exhibit great potential when optimized for power and memory efficiency, at the cost of throughput. Key design considerations and future directions, addressing the prominent tradeoff between performance, efficiency, and scalability in edge AI accelerator development are discussed in the paper. We conclude that no current design fully satisfies every edge computing constraint, highlighting the need for hybrid solutions that balance reconfigurability, power, and performance at a reduced cost.