Research and Design of Triple Modular Redundancy Technology for Processors Oriented to RISC-V Architecture

The work addresses the challenge of interference caused by high-energy radiation particles in space environments, focusing on the design and implementation of high-reliability processor technologies based on the RISC-V architecture. The objective is to overcome key technical barriers for system-level reinforcement using Triple Modular Redundancy (TMR) on RISC-V platforms. Such interference can easily disrupt the functionality of spaceborne devices, leading to severe operational errors. The proposed research aims to provide a robust and reliable foundation for improving the reliability and extending the operational lifespan of space-based systems. RISC-V-based processor design offers notable advantages, including short development cycles, low resource overhead, reduced design complexity, and full autonomy, making it both a valuable and challenging research direction. To meet the high-reliability requirements of spaceborne systems, this research investigates fault-tolerant techniques for processors, emphasizing a system-level fault-tolerant design based on triple modular redundancy. The study thoroughly examines reliability challenges in space environments, particularly the fault resilience demands placed on processors as core components. Existing processor fault-tolerant methods are reviewed, and the benefits and limitations of TMR technology in enhancing system dependability are analyzed. On this basis, a system-level faulttolerant architecture is proposed, integrating the reliability advantages of TMR while incorporating an optimized synchronization control algorithm to further improve the reliability and stability of spaceborne computing systems.