A Flip-Flop Movement Strategy Based on Lagrange Function for Timing-Driven Detailed Placement

Timing is critical in Very Large Scale Integrated (VLSI) circuit design, which is highly dependent on timing optimization during the placement phase. Recently, timingdriven detailed placement addresses early and late timing violations in circuits by adopting various cell movement techniques to relocate combinational cells and Flip-Flops (FFs). However, since Flip-Flops involve multiple timing paths, FFs' position optimization is more complex and thus often neglected in resolving late timing violations. In this paper, we propose a Lagrangian function-based Flip-Flop movement method to mitigate late timing violations in circuits, which analyzes in detail the effect of Flip-Flop movement on the negative slack values of pins in the nearby net and incorporates timing constraints in the objective function to improve accuracy. We also integrate the proposed Flip-Flop movement strategy into the state-of-the-art timing-driven detailed placer Rsyn [10], [11] to address its shortcoming of neglecting register movement during the optimization of late timing violations. Experimental results show that our approach achieves remarkable timing improvement without compromising total wirelength and routability, compared with the state-of-the-art timing-driven detailed placer.