AutoRRAM: An Agile RRAM Compiler Featuring Simultaneous Layout/Netlist Generation and Cross-Technology Migration

As a next-generation non-volatile memory technology, Resistive Random Access Memory (RRAM) has garnered significant attention due to its advantages in high-speed read/write operations, high-density integration, and low power consumption. However, conventional design methodologies struggle to meet the rapid iteration demands of RRAM IP cores. To address this challenge, we propose AutoRRAM, an agile development framework-based compiler that enables automated design of RRAM memory arrays and peripheral circuits (including decoders and multiplexers) through parametric modeling, supporting automatic generation of physical layouts. As the first Python-based portable development platform in this domain, AutoRRAM innovatively achieves process migration across different technologies from 40nm to 55nm and 28nm, while also supporting dynamic switching between memory storage and in-memory computing modes. Experimental results demonstrate that compared with traditional full-custom design approaches, AutoRRAM reduces the design cycle from several months to less than an hour while maintaining comparable circuit and area performance. This compiler, which combines high efficiency with scalability, not only provides a standardized design framework for RRAM technology research but also facilitates the industrial application process of RRAM IP cores through its user-friendly development paradigm.