Design and optimization of 6T SRAM cell at different technology nodes using CMOS for Low power and high-speed neural network computation

The increasing demand for energy-efficient and high-speed neural network inference has driven significant advancements in memory technology. The paper focuses on the design and optimization of a 6T SRAM cell across various technology nodes (45nm & 22nm) and evaluates how scaling down the technology node affects the performance, average power, stability, and delay of the cell using predictive technology model (PTM) files. These parameters are analyzed for their use in low-power and high-speed neural network computation. The static noise margin (SNM) for hold, read and write stability is analyzed by butterfly curve method. Through extensive simulations with cadence virtuoso, a read delay of 45nm as compared with 90nm is reduced by 58.7%, a further read delay of 22nm is reduced by 55.7% compared to the 45nm node. The write delay increases by about 7.2% when moving from 90nm to 45nm and the write delay decreases by about 7.6% when moving from 45nm to 22nm.