A low power Schmitt-trigger driven 8T SRAM cell design with lower leakage current using CMOS Technology

An innovative single-ended 8T SRAM cell using Schmitt trigger technology is introduced in this paper, offering significant improvements in write and read static noise margins (SNM) while maintaining low power consumption among the compared SRAM cells. Monte Carlo 500 simulations confirm its robust performance under process variations. The implementation of this design is carried out in Cadence Virtuoso with the GPDK 45 nm CMOS technology. Additionally, it reduces power consumption by up to 88.74×, improves write ability and read stability by 1.12× and 1.2×, respectively, and reduces read and write access times by 21.4× and 8.09×. A novel figure of merit is also introduced to comprehensively evaluate delay, power dissipation, stability and lower leakage current.