RepPart: An Efficient Partitioning Framework with Replication Technique for MFS

The design of large-scale digital integrated circuits (ICs) increasingly relies on logic verification, with FPGA-based hardware emulation emerging as a critical component. Efficient partitioning of the circuit netlist and its mapping to a multi-FPGA system (MFS) for emulation has become a key research focus. Due to limited I/O resources, each FPGA is typically connected directly to only a few other FPGAs. Consequently, signal transmission must pass through intermediate FPGAs, which act as hops in the signal path. This phenomenon increases signal delay and degrades overall system performance. This paper introduces RepPart, an efficient partitioning algorithm for multi-FPGA systems designed to simultaneously address multiple constraints. Building on multiple initial partitioning methods, the process is optimized by integrating the fast candidate partition propagation algorithm and the distant root node selection algorithm. Furthermore, solution quality is enhanced by replicating a limited number of critical nodes during the refinement process. Compared to existing approaches, RepPart achieves higher-quality zero-hop solutions in significantly less time.