DATIS: DRAM Architecture and Technology Integrated Simulation

Recent advances in DRAM technologies and large-dataset applications in data centers make both academic and industrial researchers eager to explore DRAM’s novel usage and cross-disciplinary DTCO (design and technology co-design) spaces, as illustrated by recent studies of the PIM (Processing-In-Memory) or RowHammer effect etc. This evolving landscape has created a pressing need for systematic testing and validation of those emerging DTCO studies. However, previous DRAM simulators have lacked joint modeling of device and architecture, impeding effective simulation of these DTCO designs. To address this gap, we introduce DATIS (DRAM Architecture and Technology Integrated Simulator), a tool that effectively connects architectural design and the complexities of DRAM technology. DATIS addresses two critical challenges: abstracting technology intricacies and establishing connections between architectural activities and device-level process structures. This versatile tool empowers researchers to unlock the latent capabilities of DRAM and provides manufacturers with a platform to experiment with new processes and architecture co-design. To the best of our knowledge, DATIS is the first DRAM simulator in academia that integrates architecture and technology modeling. We build DATIS upon Ramulator, a well-known open source DRAM simulator for architecture-level modeling, and thus it can support a wide range of DRAM specifications, including DDRx, LPDDR5, GDDR6, and HBM2&3 etc. Our experiments demonstrate DATIS’s efficacy and precision through three compelling case studies, addressing pivotal facets of DRAM technology, including storage, reliability, and computation.