Design Space Folding: A "Free-lunch" Add-on for Efficient Design Convergence in Transistor Sizing

Automatic transistor sizing in circuit design remains a significant challenge. While Bayesian optimization (BO) has shown promise, its optimization process is hindered by large design spaces for most practical circuits, particularly as technology nodes shrink. Inspired by professional analog circuit design workflows where key factors are identified and prioritized in optimization, we propose Design Space Folding (DSFold) to imitate such a process to assist design convergence. The optimization is initially conducted in a folded design space, allowing design points to escape saddle points and converge quickly toward potential global optima, with the design space progressively unfolding to consider all variables. We assess DSFold by equipping it with many state-of-the-art (SOTA) transistor sizing optimizers on multiple analog circuit benchmarks and show a 1.05×-5.34× speedup and a 1.10×-2.91× convergence performance improvement compared to their original forms with almost zero extra cost (only ∼3% computational overhead), achieving significant improvements while maintaining the "free-lunch" advantage.