FPGA based Matrix Multiplication Accelerator

The demand for high-speed matrix multiplication continues to grow due to recent developments in images processing, graphics processing, digital signal processing and communication via wireless network. Hence, designing an effective matrix multiplication accelerator is crucial which can perform fast multiplication operation since multiplication on hardware requires much more hardware resources and computational time. To design such kind of hardware, the number of partial products generations must be kept to a minimum, which reduces the amount of add operations and shortens the time it takes to do the multiplication operation. The factor canonical signed digit (FCSD) approach can lower the number of partial products formed during multiplication and eliminate the need for dedicated multiplier. This paper presents a field programmable gate array (FPGA)-based matrix multiplication accelerator that uses FCSD method within a pipeline structure, with a comparative study performed on two distinct Xilinx FPGA platforms: Zynq-7000 and Artix-7.