A Rail-to-Rail Input NS-Pipelined-SAR ADC With Self-Boosted Input Impedance and Reused Residue Amplifier for Biosignal Acquisition

This article presents an energy-efficient 3rd-order noise-shaping (NS) pipelined-SAR ADC (NSP-ADC) with rail-to-rail input range and high input impedance over-the-bandwidth for biosignal acquisition. The two-stage pipelined-SAR architecture provides high resolution with low oversampling ratio (OSR) and inherent wide linear input range. In the proposed self-boosted input impedance technique, the previous sampled charge is exactly recovered without additional charging circuits, significantly improving the input impedance with high energy and hardware efficiency. Besides, to fit in the NS-pipelined-SAR architecture, the charge-sharing-based sampling noise cancellation (SNC) is presented. It boosts the input impedance further by reducing sampling capacitance and improves linear input range by nonlinearity cancellation. In addition, benefiting from the compact charge-sharing-based NS, the interstage residue amplifier (RA) of the pipelined-SAR ADC is reused by the SNC and NS circuits of both stages to further save power. Fabricated in 180-nm 1P6M standard CMOS, the proposed NSP-ADC shows an input impedance of >150 M $\Omega $ over 1 kHz. With a low OSR of 10, it achieves the SNDR and SFDR of 87.3 and 95.2 dB, respectively, with a 1.96-V_pp differential input, while only consuming $7~{\mu }$ W at a sampling rate of 20 kS/s.