Design and Implementation of an Adaptive FPGA-Based Traffic Light Control System Using Verilog

This paper describes an adaptive traffic light control system using FPGAs and Verilog. It features a 6-state finite state machine that adjusts signal timing in real time based on traffic, pedestrian, and emergency inputs. The system achieves sub-10 ns latency, reduces vehicle delay by 36%, and uses 35% less power than microcontroller-based systems. Simulations confirm correct operation and fault recovery. The design is scalable, energy-efficient, and well-suited for smart city traffic management.