Time-Symmetric Sampling to Eliminate Pulse-Width-Modulation Delay in Digital Controlled Three-Phase Inverter

In this article, a time-symmetric sampling method is proposed to eliminate the pulse-width-modulation (PWM) delay in digital PWM (DPWM) inverters. To attain this objective, an analysis of the sampling’s impact on the PWM delay is conducted first. Based on the discrete-time analysis, different sampling methods cannot actually reduce time delay but rather introduce ripples in the sampling signal. In DPWM inverters with triangular carriers, due to time-symmetric characteristics, these ripples can eliminate the PWM delay equivalently. Then, the time-symmetric sampling DPWM (TSS-DPWM) is proposed by making the sampling time points meet the time symmetry condition. With the proposed method, the complete elimination of PWM delay can be achieved without increasing the sampling frequency. Finally, a comparison with existing DPWM methods is conducted through theoretical analysis, simulation, and experimental validation. The stability of the proposed TSS-DPWM inverter is equivalent to that of a multisampling DPWM inverter operating at an infinite sampling frequency. Meanwhile, the sampling frequency and calculation amount remain consistent with those of the traditional dual-sampling DPWM inverter. The aforementioned analyses and comparisons are validated by both simulation and experiment results.