The Fake-Busy and True-Idle Problems of Running Graph Applications on Chiplet-Based Multi-Cores

We introduce the fake-busy and true-idle problems encountered when running large graph workloads on chipletbased Out-of-Order (OoO) multi-cores. Caused by high interchiplet communication latency and irregular memory access patterns, these issues lead to inefficient use of core pipeline resources such as the Reorder Buffer (RoB) and Load Queue (LQ). Our evaluation shows that reducing RoB and LQ sizes has minimal impact on application performance, revealing new performance optimization opportunities for large graph workloads.