A Spike Sorting SoC With Δ-Based Spike Detection and End-to-End Implementation of Autoencoder Feature Extraction Using Analog CIM

To process the substantial data generated from on-chip neural recordings, a robust spike sorting (SS) system-on-chip (SoC) with minimal latency is essential to ensure timely response in closed-loop brain–computer interface (BCI) applications. In this article, we report a $\Delta $ -based SS SoC featuring the first on-chip incorporation of analog computing-in-memory (CIM) end-to-end binary autoencoder neural network (B-AENN) feature extraction to lower computation energy while maintaining high accuracy. The use of $\Delta $ -spike-signals in this work not only improves the noise resilience of the SS system but also provides a better foundation for feature extraction, leading to enhanced accuracy. The integration of B-AENN enables a more adaptive approach, in comparison to predefined methods, to extract features, especially for closely resembling spikes. Furthermore, by relocating the spike detection and feature extraction processes to the analog domain, our proposed system overcomes the analog-to-digital converter (ADC) conversion bottlenecks in increasingly dense channels. Fabricated using a 65-nm CMOS technology process, the prototype chip facilitates exceptional performance with 5.1- $\mu $ s computational latency, making it ideal for closed-loop, real-time applications and achieving a classification accuracy of 94.54% while consuming $3.11~{\mu }$ W/ch, representing the highest reported on-chip classification accuracy to date.