Optimization of Object Detection Capabilities in a FPGA SoC Using the Yolo-Tiny Model

This research aims to optimize object detection capabilities on the FPGA Arria 10 SoC platform using the YOLO-tiny model. The system integrates hardware and software to optimize data flow with OpenCL. The study uses half-precision floating-point data to balance performance and hardware resource savings, significantly reducing resource requirements without compromising accuracy. Additionally, the system incorporates a data flow pipeline approach. Experiments on a standard dataset demonstrate that the system achieves an average processing speed of 220 ms per frame with performance improvements ranging from 15% to 20% when we implemented on-board FPGA Arria 10. These results validate the system's efficiency and highlight its potential applications in AI systems designed for edge devices, which demand high performance while conserving energy and meeting the requirements of real-time applications.