A Cost-Efficient Implementation of an SSVEP-Based Brain-Controlled Robotic Arm System

This study presents a low-cost FPGA implementation of a single channel SSVEP-BCI system, achieved real-time control of the robotic arm. The proposed architecture integrates a hybrid preprocessing chain that merges differential filtering with a coefficient-symmetric FIR design, achieving the reduction in hardware resource of 42.8%. A radix-4 DIF FFT module is implemented using a four-stage pipelined SDF structure, optimized by a surface-fitting-based approximate complex multiplier to achieve 70.6% reduction in DSPs resource while preserving spectral analysis precision. This system demonstrates the accuracy of the classification 83.4% with 176mW power consumption on Xilinx Artix-7 FPGA (xc7a35tcsg324-1). Experimental validation using both proprietary datasets and open datasets confirms superior performance. Compared to conventional PC-based solutions in robotic arm control tasks, this study establishes a hardware-efficient framework that effectively balances real-time operation, classification accuracy, and low-power constraints for practical BCI deployments.