A Power-Efficient Analog Integrated Decision Tree Classifier for Machine Predictive Maintenance Classification

This study introduces an analog integrated decision tree classifier specifically engineered for real-time machine predictive maintenance while maintaining minimal power usage. Fabricated with the TSMC 90nm CMOS process, the design leverages sub-threshold analog circuitry to secure an exceptionally low power consumption of 528nW and a classification throughput of 380K inferences per second. When evaluated using a dataset representative of machine operational conditions, the classifier achieved an average accuracy of 94.51% and consistently performed well despite fluctuations in process, voltage and temperature. This approach provides efficient, real-time, edge-based classification in industrial settings, thereby facilitation early fault detection and enabling proactive maintenance strategies.