SHA-256 Hash Generator in Verilog HDL

An implementation of SHA-256 hash generator is presented. A block has been described in Verilog HDL. A generator code is written with basic logical and arithmetic operations to create a easily-synthesizable block. A design process a 512-bit block in 67 cycles. The generator is tested in simulations with the test vectors and reference digests published by NIST. The simulation testbench has been designed in SystemVerilog. The design passed all test cases used.