An LLM-assisted Analog IC Design Tool with Automatic Topology Selection and Circuit Sizing

Recently, Large Language Models (LLMs) have gained a rising interest in different domains, including code generation for digital IC design. However, building an effective LLM for analog IC design is challenging because a valid analog circuit cannot be constructed by just randomly combining some codes. In this paper, an LLM-assisted analog IC design tool is presented to support from automatic topology selection to circuit sizing in a conversational manner. This tool allows designers to express their requirements through natural language rather than being restricted by a fixed template, which decreases the learning curve of using such an automation tool. In order to meet users’ intentions, a subsequent ANN-based sizing process is invoked to further refine the "nearest" circuit obtained from the LLM without tedious iterations. Compared with previous works, the proposed LLM-assisted tool is more efficient and convenient while generating reliable analog designs to meet users’ requirements. Our experiments show that the tool can generate workable circuits with short execution time.