VLSI Implementation of an Energy-Efficient Approximate Softmax Function for Deep Neural Networks Using the PDU Technique

This paper focuses an optimized softmax function designed specifically for energy-efficient deployment in deep neural networks (DNNs), targeting platforms with limited processing power such as edge devices and embedded systems. The proposed solution is based on a Pipelined Division Unit (PDU) architecture developed using Verilog HDL, aiming to reduce power consumption and hardware complexity while maintaining functional accuracy. By incorporating approximation strategies, the softmax computation is simplified for hardware realization, making it well-suited for applications in low-power domains like IoT, wearables, and autonomous technologies. Implementation on a Virtex 6VLX75T-1FF784 FPGA shows a marked improvement compared to conventional softmax methods, with significant reductions in resource usage-such as logic blocks, LUTs, and slices-as well as lower propagation and gate delays. These enhancements contribute to faster execution times, reinforcing the design's applicability to real-time, power-sensitive AI workloads.