Modular and Power-Efficient Matrix Multiplication: Implementation of Strassen's Algorithm

This paper presents a hardware implementation of 32-bit matrix multiplication using Strassen's algorithm, targeting improvements in speed, power efficiency, and chip area. Strassen's method reduces the number of required multiplications by dividing matrices recursively into smaller blocks, achieving a computational complexity of approximately $\mathrm{O}\left(\mathrm{n}^{2}. 81\right)$ compared to the conventional $\mathrm{O}\left(\mathrm{n}^{3}\right)$ method. The design is implemented in Verilog and synthesized using 90 nm SAED technology. Comparative evaluation shows a 30 % reduction in area, 20 % savings in power, and 42 % improvement in timing over traditional matrix multiplication. These improvements construct the design fit for super-computing applications including steganography, artificial intelligence, and display adapter, where large-scale matrix operations are general. The work shows that a recursive, hardware-aware approach can critically accelerate matrix computation while remaining are agreeable with 32-bit architectures.