Design of Ternary Multiplier Using Multiplexers in GNRFET Technology

In this work, the design of ternary logic circuits using graphene nanoribbon field-effect transistors (GNRFETs) is presented. Ternary is a form of multiple valued logic (MVL) that offers advantages over conventional binary due to its lower power dissipation and power delay product stemming from lower interconnect count and area. GNRFETs are favored than silicon MOSFETs for logic designs because of their superior thermal, mechanical, and electrical properties. Furthermore, the capability to alter threshold voltages of GNRFETs by altering the GNR width makes them ideal for voltage-mode multi-threshold circuit design. This study demonstrates the efficient design of ternary schematics utilizing GNRFETs varying GNR dimer line to control GNR width and thus GNRFET threshold voltage. A ternary multiplier designed using GNRFETs at the 32 nm technology node shows approximately a 37.67% reduction in delay and a 35.31% reduction in power consumption compared to existing CNTFET design.